1. Field of the Invention
The present invention relates to a semiconductor package apparatus having a redistribution layer, and more particularly, to a semiconductor package apparatus having a redistribution layer for reducing the size and thickness of the semiconductor package apparatus and for reducing the number of fabrication processes in order to improve productivity.
2. Description of the Related Art
In general, packaging processes are used to seal semiconductor chips having designed micro-circuits using a sealing material such as plastic resins, ceramic materials, or the like so that the semiconductor chips may be properly installed in electronic devices. Thus, these packaging processes are important to ensure that the semiconductors and resulting electronic devices are part of reliable final consumer products.
A semiconductor package apparatus fabricated using such packaging processes can protect semiconductor chips from outer environments. The semiconductor package apparatus should connect the semiconductor chips to parts of the semiconductor package apparatus while allowing heat generated during operations of the semiconductor chips to be dispersed in order to both secure the chips to the package apparatus and enhance the thermal and electrical performances of the semiconductor chips.
Technology for stacking semiconductor chips in a semiconductor package apparatus has been developed utilizing wires to transmit and receive electrical signals between the semiconductor chips and external terminals. In this case, a spacer tape is often used between a semiconductor chip and a neighboring semiconductor chip in order to secure a space necessary for wire bonding. However, the use of spacer tape increases the stack height of the semiconductor chips and adds an additional process of attaching the spacer tape during fabrication of the semiconductor packages. As a result, productivity may be decreased.